High Speed Serial Communications
Next generation digital interface standards (serial, memory, display etc.) are pushing the limits of today’s compliance and debug tools posing several high speed Tx and Rx design challenges including
- Limited signal access due to smaller device geometries
- Bus behavior with new power-saving schemes
- Validating new signal encoding and equalization capability in signaling interfaces
- So many electrical validation tests, so little time!
Tektronix provides automated measurement suites that speed up PHY validation cycles and ensure consistency. Speed up debugging with tools like Protocol Decoding and Visual Trigger when compliance measurements fail. Identify jitter & noise from sources such as crosstalk or other multi-lane noise coupling.
STANDARDS AND TECHNOLOGIES
Featured Content
Understanding and Characterizing Timing Jitter Primer
This 24-page primer offers straightforward, practical techniques for making timing jitter measurements without the need for complex statistical calculations.
Anatomy of an Eye Diagram
This application note discusses different ways that information from an eye diagram can be sliced to gain more insight. It also discusses some basic ways that transmitters, channels, and receivers are tested.
e-Guide to High Speed Interface Standards
This FREE e-Guide will help you learn more about design challenges for testing PCIe 4.0, SAS, SuperSpeed USB, and DDR4 standards. You get quick access to technical resources that will help you understand design challenges and pick the right solution for your test needs.
Library
| Title |
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| PCI Express® Transmitter PLL Testing — A Comparison of Methods Overview of significant methods for performing PLL Testing |
| Probing Tips for High Performance Design and Measurement Learn how to identify common signal integrity problems experienced in high speed and mobile designs, modeling techniques used to study and de-embed the effects of probing, probing considerations for low power circuits and much more in this detailed application note for high performance designs. |
| High Speed Interface StandardsThis e-Guide will help you learn more about design challenges for testing PCIe 4.0, SAS, SuperSpeed USB, and DDR4 standards. Within the pages of the eGuide you will also get quick access to technical resources that will help you understand design challenges and pick the right solution for your test needs. |
| Remote Head Acquisition Improves High Speed Serial Measurement Learn how to maximize the margin in your signal integrity measurements. |
| Fast+ Efficient Solutions for DVI Conformance Measurement Challenges Tektronix provides all the DVI measurement solutions you need, ranging from high-bandwidth digital phosphor oscilloscopes (DPO) to probes to application-specific software. Tektronix has solved tough measurement problems like jitter and eye diagram tests to assemble a DVI solution that automates and simplifies your work. |
| Characterizing an SFP+ Transceiver at the 16G Fibre Channel Rate Measurements needed to test an SFP+ transceiver to the 16G Fibre Channel standard. |
| Title | |
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| Demystify MIPI D-PHY and C-PHY Transmitter and Receiver Physical Layer Test | During this webinar, you'll gain an understanding of MIPI test challenges for both MIPI high-speed physical layers and useful tips and technical insights into characterizing and validating design compliance. |
| How to Address Your Toughest Serial Bus Design Challenges with EDA and Measurement Correlation | This Tektronix webinar will teach engineers how to use modeling tools to correlate simulations with high-speed physical layer measurements on Serial Bus Standards using the DPO/MSO70000 Series Oscilloscopes. |