DDR3 and LPDDR3 Measurement and Analysis
Get more visibility into your memory designs with the Tektronix DDR3/LPDDR3 Automated Conformance package (Opt. 6-CMDDR3) and DDR3/LPDDR3 Measurement and Analysis function (Opt. 6-DBDDR3) on the 6 Series MSO. The integration of the DDR software, oscilloscope, high-performance analog and digital probes lets you perform detailed, accurate amplitude, timing, and eye diagram measurements on your DDR designs to verify compliance with the Joint Electronic Device Engineering Council (JEDEC) electrical and timing specifications. The digital probes help get insight on the control signals of the DDR bus. The 12-bit analog-to-digital converters in the 6 Series MSO deliver high-precision measurement data with the lowest noise in the industry to let you achieve new levels of debugging efficiency and measurement reliability.
Complete test coverage and fully automated conformance testing of DDR3 and LPDDR3 measurements as per the specification, including Eye diagram test on data and clock.
Ability to simultaneously define Read and Write searches and perform specific DDR measurements on the qualified bursts over long record lengths.
Ability to set voltage threshold levels per measurement as per the specification.
Intuitive user interface and workflow to configure and perform DDR electrical validation.
Easily switch from Conformance test environment to Debug environment on the scope to get deeper insights into test failures.
- Optionally save setup files in Conformance test suite, to be able to recall the scope state post execution.
Automated report generation saves measurements, test results, and waveform images in .MHT, .CSV or .PDF file format. CSV format helps to parse and customize the test reports as per users’ needs
Supports a wide range of interposers for different memory standards, along with best-in-class probes, to meet signal integrity requirements.
DDR3/LPDDR3 automated testing with Opt 6-CMDDR3
Opt. 6-CMDDR3 solution lets you perform automated DDR3 and LPDDR3 conformance testing. This solution works in conjunction with Opt. 6-DDDR3 to add specific measurements, configure these measurements and fetch the results post analysis. This helps the user to avoid manually save and recall scope setup files. The python sequencer enables fast execution of 100+ measurements, ensures test validation in completed quickly.
The DUT panel lets you choose the device type and device profile which includes the speed grade supported by the DDR device and configure the Vdd and Vref settings.
- Timing measurements
- tRPRE measures the width of the Read burst preamble. This is measured from the exit of tristate to the first driving edge of the differential strobe.
- tWPRE measures the width of the Write burst preamble. It is measured from the exit of tristate to the first driving edge of the differential strobe.
- tPST measures the width of Read or Write burst postamble. It is measured from the last falling edge crossing the mid reference level to the start of an undriven state (as measured by a rising trend per JEDEC specification).
- Hold Diff measures the elapsed time between the designated edge of the single-ended waveform and the designated edge of a differential waveform. The measurement uses the closest single-ended waveform edge to the differential waveform edge that falls within the range limits.
- Setup Diff measures the elapsed time between the designated edge of a single-ended waveform and when the differential waveform crosses its own voltage reference level. The measurement uses the closest single-ended waveform edge to the differential waveform edge that falls within the range limits.
- tCH(avg) measures the average high pulse width calculated across a sliding 200 cycle window of consecutive high pulses.
- tCK(avg) measures the average clock period across a sliding 200-cycle window.
- tCL(avg) measures the average low pulse width calculated across a sliding 200 cycle window of consecutive low pulses.
- tCH(abs) measures the high pulse width of the differential clock signal. It is the amount of time the waveform remains above the mid reference voltage level.
- tCL(abs) measures the low pulse width of the differential clock signal. It is the amount of time the waveform remains below the mid reference voltage level.
- tJIT(duty) measures the largest elapsed time between tCH and tCH(avg) or tCL and tCL(avg) for a 200-cycle window.
- tJIT(per) measures the largest elapsed time between tCK and tCK(avg) for a 200-cycle sliding window.
- tJIT(cc) measures the absolute difference in clock period between two consecutive clock cycles.
- tERR(n) measures the cumulative error across multiple consecutive cycles from tCK(avg). It measures the time difference between the sum of clock period for a 200-cycle window to n times tCK(avg).
- tERR(m-n) measures the cumulative error across multiple consecutive cycles from tCK(avg). It measures the time difference between the sum of clock periods for a 200-cycle window to n times tCK(avg).
- tDQSCK measures the strobe output access time from differential clock. It is measured between the rising edge of clock before or after the differential strobe Read preamble time. The edge locations are determined by the mid-reference voltage levels.
- tCMD-CMD measures the elapsed time between two logic states.
- tCKSRE measures the valid clock cycles required after Self Refresh Entry (SRE) command. Changing the input clock frequency or the supply voltage is permissible only after tCKSRE time when the SRE command is registered.
- tCKSRX measures the valid clock cycles required before the Self Refresh Exit (SRX) command. Changing the input clock frequency or the supply voltage is permissible provided the new clock frequency or supply voltage is stable for the tCKSRX time prior to SRX command.
- Amplitude measurements
- AOS measures the total area of the signal above the specified reference level.
- AUS measures the total area of the signal below the specified reference level.
- Vix(ac) measures the differential input cross-point voltage measured from the actual crossover voltage and its complement signal to a designated reference voltage. This is measured on a single-ended signal.
- AOS Per tCK measures the total area of the signal that crosses the specified reference level calculated over consecutive periods. It is applicable to clock and address/command waveforms only.
- AUS Per tCK measures the total area of the signal that crosses the specified reference level calculated over consecutive periods. It is applicable to clock and address/command waveforms only.
- AOS Per UI measures the total area of the signal that crosses the specified reference level calculated over consecutive unit intervals. It is applicable to data and data strobe waveforms only.
- AUS Per UI measures the total area of the signal that crosses the specified reference level calculated over consecutive unit intervals. It is applicable to data and data strobe waveforms only.
|Speed (MT/s)||800, 1066, 1333, 1600, 1866, and 2133||333, 800, 1066, 1200, 1333, 1466, 1600, 1866 and 2133|
|Max slew rate||10 V/ns||8 V/ns|
|Typical V swing||1 V||0.6 V|
|20-80 risetime||60 ps||45 ps|
|Report||HTML and PDF format|
|Source support||Live analog signals, reference waveforms, and math waveforms|
|De-embedding support||Filter file using math subsystem|
|Oscilloscope||6 Series MSO oscilloscope with minimum bandwidth of 4 GHz (6-BW-4000) for debug and a recommended bandwidth of 8 GHz (6-BW-8000) for DDR3/LPDDR3 automated conformance testing.|
|Operating system||6-WIN (removable SSD with Microsoft Windows 10 operating system).
Optional - Required only for DDR3/LPDDR3 automated conformance testing
|DDR3 and LPDDR3 Automated Compliance Solution for 6 Series MSO 1||6-CMDDR3||New instrument license|
|SUP6-CMDDR3-FL||Floating license 2|
|DDR3 and LPDDR3 Analysis and Debug Solution for 6 Series MSO 3||6-DBDDR3||New instrument license|
|SUP6-DBDDR3-FL||Floating license 2|
1DDR3 and LPDDR3 Automated Compliance Solution for 6 Series MSO requires 6-DBDDR3 and 6-DJA as a pre-requisite for running DDR and Eye diagram measurements.
2Floating licenses are transferrable from any 6 Series MSO to any other 6 Series MSO, for use of one instrument at a time.
3Additional information about DDR analysis is available athttps://www.tek.com/ddr-test-validation-and-debug.
Recommended probes and accessories
|TDP7708 Tri-mode probe with P77STFLXB adapters||Two probes are required for testing a DUT with DQ and DQS.
Three probes are required for testing a DUT with DQ, DQS and clock.
|TLP058||One probe is required for probing CS, RAS, CAS, and WE lines.|
|TDP3500||One probe is required for CS as Analog signal.|
|DDR3: x4, x8, 16 socketed, solder-down and direct attach interposers||Sold through Tektronix and Nexus Technologies 1|
|LPDDR3: BGA and PoP interposers|
1Contact your local Tektronix representative for details.